x86 Instruction Set Reference

CVTPD2PS - Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values

Opcode Mnemonic Description
66 0F 5A /r CVTPD2PS xmm1, xmm2/m128 Convert two packed double-precision floating-point values in xmm2/m128 to two packed singleprecision floating-point values in xmm1.
Description

Converts two packed double-precision floating-point values in the source operand (second operand) to two packed single-precision floating-point values in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The result is stored in the low quadword of the destination operand, and the high quadword is cleared to all 0s. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
Operation 
Destination[0..31] = ConvertDoubleToFloat(Source[0..63]);
Destination[32..63] = ConvertDoubleToFloat(Source[64..127]);
Destination[64..127] = 0;
SIMD Floating-Point Exceptions
Overflow,Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0)For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#NMIf TS in CR0 is set.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
Real-Address Mode Exceptions
#GP(0)If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
#GP(0)If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NMIf TS in CR0 is set.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode
#PF(fault-code)For a page fault.
Instruction Latency Throughput Execution Unit
CPUID0F3n/0F2n0F3n/0F2n0F2n
CVTPD2PS xmm, xmm11/102/2FP_ADD MMX_SHFT