x86 Instruction Set Reference

CVTPI2PS - Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values

Opcode Mnemonic Description
0F 2A /r CVTPI2PS xmm, mm/m64 Convert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm.
Description

Converts two packed signed doubleword integers in the source operand (second operand) to two packed single-precision floating-point values in the destination operand (first operand). The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. The results are stored in the low quadword of the destination operand, and the high quadword remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.
Operation 
Destination[0..31] = ConvertIntegerToFloat(Source[0..31]);
Destination[32..63] = ConvertIntegerToFloat(Source[32..63]);
//high quadword of destination remains unchanged
SIMD Floating-Point Exceptions
Precision.
Protected Mode Exceptions
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#NMIf TS in CR0 is set.
#MFIf there is a pending x87 FPU exception.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UDIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
Real-Address Mode Exceptions
GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NMIf TS in CR0 is set.
#MFIf there is a pending x87 FPU exception.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode
#PF(fault-code)For a page fault.
#PF(fault-code)For a page fault.
Instruction Latency Throughput Execution Unit
CPUID0F3n/0F2n/069n0F3n/0F2n/069n0F2n
CVTPI2PS xmm, mm12/11/32/4/1MMX_ALU FP_ADD MMX_SHFT