x86 Instruction Set Reference

FINIT/FNINIT - Initialize Floating-Point Unit

Opcode Mnemonic Description
9B DB E3 FINIT Initialize FPU after checking for pending unmasked floating-point exceptions.
DB E3 FNINIT Initialize FPU without checking for pending unmasked floating-point exceptions. See the IA-32 Architecture Compatibility section below.
Description

Sets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU control word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared (no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all tagged as empty (11B). Both the instruction and data pointers are cleared.

The FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing the initialization; the FNINIT instruction does not.

The assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT instruction), and the processor executes each of these instructions in separately.

If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.

Operation
FPUControlWord = 0x37F;
FPUStatusWord = 0;
FPUTagWord = 0xFFFF;
FPUDataPointer = 0;
FPUInstructionPointer = 0;
FPULastInstructionOpcode = 0;
FPU flags affected

C0, C1, C2, C3 set to 0.

IA-32 Architecture Compatibility

FINIT/FNINIT: Initialize Floating-Point Unit (x86 Instruction Set Reference)

Floating-Point Exceptions
None.
Protected Mode Exceptions
#NMEM or TS in CR0 is set.
Real-Address Mode Exceptions
#NMEM or TS in CR0 is set.
Virtual-8086 Mode Exceptions
#NMEM or TS in CR0 is set.